<?xml version="1.0"?>
<!DOCTYPE flagsdescription SYSTEM "http://www.spec.org/dtd/cpuflags2.dtd">

<flagsdescription>

<!--
######################################################################################################
       This platform flags file is supplied as an example. Please document bios/firmware settings in your
       systems that are set to non-default values for performance runs.  

       You MUST change the filename tag just below; at the very least, change "Invalid" to your company name.
######################################################################################################
-->

<filename>Supermicro-Platform-Settings-V1.2-Turin-revG</filename>

<title>SPEC CPU Platform Settings for Supermicro Systems</title>

<os_tuning>
<![CDATA[
<dl>

<dt><b>kernel.randomize_va_space</b> (ASLR)</dt>
  <dd>
    This setting can be used to select the type of process address space randomization. 
    Defaults differ based on whether the architecture supports ASLR, whether the kernel 
    was built with the CONFIG_COMPAT_BRK option or not, or the kernel boot options used.<br>
    Possible settings:
    <ul>
      <li>0: Turn process address space randomization off.</li>
      <li>1: Randomize addresses of mmap base, stack, and VDSO pages.</li>
      <li>2: Additionally randomize the heap. (This is probably the default.)</li>
    </ul>
    Disabling ASLR can make process execution more deterministic and runtimes more consistent.
    For more information see the <code>randomize_va_space</code> entry in the
    <a href="https://www.kernel.org/doc/Documentation/sysctl/kernel.txt">Linux sysctl documentation</a>.
  </dd>

  <dt><b>Transparent Hugepages (THP)</b></dt>
  <dd>
    THP is an abstraction layer that automates most aspects of creating, managing,
    and using huge pages. It is designed to hide much of the complexity in using
    huge pages from system administrators and developers.  Huge pages
    increase the memory page size from 4 kilobytes to 2 megabytes. This provides
    significant performance advantages on systems with highly contended resources
    and large memory workloads. If memory utilization is too high or memory is badly
    fragmented which prevents hugepages being allocated, the kernel will assign
    smaller 4k pages instead. Most recent Linux OS releases have THP enabled by default.<br>
    THP usage is controlled by the sysfs setting <code>/sys/kernel/mm/transparent_hugepage/enabled</code>.
    Possible values:
    <ul>
      <li>never: entirely disable THP usage.</li>
      <li>madvise: enable THP usage only inside regions marked MADV_HUGEPAGE using madvise(3).</li>
      <li>always: enable THP usage system-wide. This is the default.</li>
    </ul>
    THP creation is controlled by the sysfs setting <code>/sys/kernel/mm/transparent_hugepage/defrag</code>.
    Possible values:
    <ul>
      <li>never: if no THP are available to satisfy a request, do not attempt to make any.</li>
      <li>defer: an allocation requesting THP when none are available get normal pages while requesting THP creation in the background.</li>
      <li>defer+madvise: acts like "always", but only for allocations in regions marked MADV_HUGEPAGE using madvise(3); for all other regions it's like "defer".</li>
      <li>madvise: acts like "always", but only for allocations in regions marked MADV_HUGEPAGE using madvise(3).  This is the default.</li>
      <li>always: an allocation requesting THP when none are available will stall until some are made.</li>
    </ul>
    An application that "always" requests THP often can benefit from waiting for an allocation until those huge pages can be assembled.<br>
    For more information see the <a href="https://www.kernel.org/doc/Documentation/vm/transhuge.txt">Linux transparent hugepage documentation</a>.
  </dd>

  <dt><b>dirty_ratio</b></dt>
  <dd>
    This is a percentage value of total available memory that can be filled with dirty data before writing the modifications to disk. Set through "sysctl -w vm.dirty_ratio=8".
  </dd>

  <dt><b>swappiness</b></dt>
  <dd>
	This control is used to define how aggressive the kernel will swap memory pages. Increaasing the value causes swapping more frequently. The default value is 60. 
	A value of 1 tells the kernel to only swap processes to disk if absolutely necessary. This can be set through a command like "sysctl -w vm.swappiness=1"
  </dd>
 
  <dt><b>zone_reclaim_mode</b></dt>
  <dd>
	Zone_reclaim_mode allows someone to set more or less aggressive approaches to reclaim memory when a zone runs out of memory. 
	It controls whether memory reclaim is performed on a local NUMA node or other nodes. 
	To tell the kernel to free local node memory rather than grabbing free memory from remote nodes, it can be set through a command like "sysctl -w vm.zone_reclaim_mode=1".
  </dd>

  <dt><b>drop_caches</b></dt>
  <dd>
	Writing this will cause kernel to drop clean caches, as well as reclaimable slab objects like dentries and inodes. Once dropped, their memory becomes free. 
	Set through "sysctl -w vm.drop_caches=3" to free slab objects and pagecache.
  </dd>

<dt><b>CPUFreq scaling governor</b>:</dt>
 <dd>
  <p>Governors are power schemes for the CPU. It is in-kernel pre-configured power schemes for the CPU and allows you to change the clock speed of the CPUs on the fly. On Linux systems can set the govenor for all CPUs through the cpupower utility with the following command:</p>
  <ul>
   <li>"cpupower -c all frequency-set -g governor"</li>
  </ul>
  <p>Below are govenors in the Linux kernel.</p>
  <ul>
   <li><b>performance</b>: Run the CPU at the maximum frequency.</li>
   <li><b>powersave</b>: Run the CPU at the minimum frequency.</li>
   <li><b>userspace</b>: Run the CPU at user specified frequencies.</li>
   <li><b>ondemand</b>: Scales the frequency dynamically according to current load. Jumps to the highest frequency and then possibly back off as the idle time increases.</li>
   <li><b>conservative</b>: Scales the frequency dynamically according to current load. Scales the frequency more gradually than ondemand.</li>
   <li><b>schedutil</b>: Scheduler-driven CPU frequency selection.</li>
  </ul>
 </dd>

<dt><b>tuned-adm</b>:</dt>
 <dd>
  <p>A commandline interface for switching between different tuning profiles available in supported Linux distributions. The distribution provided profiles are located in /usr/lib/tuned and the user defined profiles in /etc/tuned. To set a profile, one can issue the command "tuned-adm profile (profile_name)". Below are details about some relevant profiles. </p>
  <ul>
   <li><b>throughput-performance</b>: For typical throughput performance tuning. Disables power saving mechanisms and enables sysctl settings that improve the throughput performance of disk and network I/O. CPU governor is set to performance and CPU energy performance bias is set to performance. Disk readahead values are increased.</li>
   <li><b>latency-performance</b>: For low latency performance tuning. Disables power saving mechanisms. CPU governor is set to performance and locked to the low C states. CPU energy performance bias to performance.</li>
   <li><b>balanced</b>: Default profile provides balanced power saving and performance. It enables CPU and disk plugins of tuned and makes the conservative governor is active and also sets the CPU energy performance bias to normal. It also enables power saving on audio and graphics card.</li>
   <li><b>powersave</b>: Maximal power saving for whole system. It sets the CPU governor to ondemand governor and energy performance bias to powersave. It also enable power saving on USB, SATA, audio and graphics card.</li>
  </ul>
 </dd>

</dl>
]]>
</os_tuning>

<firmware>
<![CDATA[
<dl>

<dt><b>Determinism Control:</b></dt> 
 <dd>
  This BIOS option allows for choose AGESA determinism control. 
  AGESA is an acronym for "AMD Generic Encapsulated Software Architecture."
  AGESA is a bootstrap protocol by which system devices on AMD64-architecture mainboards are initialized, it responsible for the initialization of the processor cores, memory, and the HyperTransport controller.
  Available settings are:
  <ul>
      <li>Manual: User can customize determinism slider.</li>      

      <li>Auto (Default setting): Use the processor fused determinism control.</li>
  </ul>
 </dd>

<dt><b>Determinism Enable:</b></dt> 
 <dd>
  This BIOS option allows for Enable/Disable AGESA determinism to control performance. 
  AGESA is an acronym for "AMD Generic Encapsulated Software Architecture."
  AGESA is a bootstrap protocol by which system devices on AMD64-architecture mainboards are initialized, it responsible for the initialization of the processor cores, memory, and the HyperTransport controller.
  "Performance determinism" tells the processor to run in a consistent manner which allows consistent repeatability when doing benchmarks or performance testing. 
  The processor will run at the best performance with little deviation allowing repeatable runs. 
  Available settings are:
  <ul>
      <li>Performance: AGESA will enable 100% deterministic performance control.</li>      

      <li>Power: AGESA will not enable deterministic performance control.</li>
  </ul>
 </dd>

<dt><b>TDP Control:</b></dt> 
 <dd>
  This BIOS option is for "Configurable TDP (cTDP)", it allows user can set customized value for TDP. Available settings are:
  <ul>
	  <li>Auto (Default setting): Use the fused TDP value.</li>
	  
	  <li>Manual: Let user specifies customized TDP value.</li>
  </ul>
 </dd>

<dt><b>TDP:</b></dt> 
 <dd>
  TDP is an acronym for “Thermal Design Power.” TDP is the recommended target for power used when designing the cooling capacity for a server. 
  EPYC processors are able to control this target power consumption within certain limits. This capability is referred to as “configurable TDP” or "cTDP."
  cTDP can be used to reduce power consumption for greater efficiency, or in some cases, increase power consumption above the default value to provide additional performance.
  cTDP is controlled using a BIOS option.<br/>
<br>
  The default EPYC cTDP value corresponds with the microprocessor’s nominal TDP. For the EPYC 9355, the default value is 280W. 
  The default cTDP value is set at a good balance between performance and energy efficiency. 
  The EPYC 9355 cTDP can be reduced as low as 240W, which will minimize the power consumption for the processor under load, but at the expense of peak performance. 
  Increasing the EPYC 9355 cTDP to 300W will maximize peak performance by allowing the CPU to maintain higher dynamic clock speeds, but will make the microprocessor less energy efficient. 
  Note that at maximum cTDP, the CPU thermal solution must be capable of dissipating at least 300W or the EPYC 9354 processor might engage in thermal throttling under load.<br>
<br>
  The available cTDP ranges for each EPYC model are in the table below:
	<table>
		<tr><th>Model</th><th>Nominal TDP</th> <th>Minimum cTDP</th> <th>Maximum cTDP*</th></tr>
		<tr><th>EPYC 9965</th><th>500W</th> 		<th>450W</th> 		   <th>500W</th></tr>
		<tr><th>EPYC 9845</th><th>390W</th> 		<th>320W</th> 		   <th>400W</th></tr>
		<tr><th>EPYC 9745</th><th>400W</th> 		<th>320W</th> 		   <th>400W</th></tr>
		<tr><th>EPYC 9755</th><th>500W</th> 		<th>450W</th> 		   <th>500W</th></tr>
		<tr><th>EPYC 9655</th><th>400W</th> 		<th>320W</th> 		   <th>400W</th></tr>
		<tr><th>EPYC 9655P</th><th>400W</th> 		<th>320W</th> 		   <th>400W</th></tr>
		<tr><th>EPYC 9575F</th><th>400W</th> 		<th>320W</th> 		   <th>400W</th></tr>
		<tr><th>EPYC 9565</th><th>400W</th> 		<th>320W</th> 		   <th>400W</th></tr>
		<tr><th>EPYC 9555</th><th>360W</th> 		<th>320W</th> 		   <th>400W</th></tr>
		<tr><th>EPYC 9555P</th><th>360W</th> 		<th>320W</th> 		   <th>400W</th></tr>
		<tr><th>EPYC 9535</th><th>300W</th> 		<th>240W</th> 		   <th>300W</th></tr>
		<tr><th>EPYC 9475F</th><th>400W</th> 		<th>320W</th> 		   <th>400W</th></tr>
		<tr><th>EPYC 9455</th><th>300W</th> 		<th>240W</th> 		   <th>300W</th></tr>
		<tr><th>EPYC 9455P</th><th>300W</th> 		<th>240W</th> 		   <th>300W</th></tr>
		<tr><th>EPYC 9375F</th><th>320W</th> 		<th>320W</th> 		   <th>400W</th></tr>
		<tr><th>EPYC 9355</th><th>280W</th> 		<th>240W</th> 		   <th>300W</th></tr>
		<tr><th>EPYC 9355P</th><th>280W</th> 		<th>240W</th> 		   <th>300W</th></tr>
		<tr><th>EPYC 9135</th><th>200W</th> 		<th>200W</th> 		   <th>240W</th></tr>
		<tr><th>EPYC 9115</th><th>125W</th> 		<th>120W</th> 		   <th>155W</th></tr>
		<tr><th>EPYC 9015</th><th>125W</th> 		<th>120W</th> 		   <th>155W</th></tr>
	</table>
    * cTDP must remain below the thermal solution design parameters or thermal throttling could be frequently encountered.
 </dd>
 
<dt><b>IOMMU:</b></dt> 
 <dd>
  The I/O Memory Management Unit (IOMMU) extends the AMD64 system architecture by adding support for address translation and system memory access protection on DMA transfers from periph-eral devices.
  IOMMU also helps filter and remap interrupts from peripheral devices.
  Available settings are:
  <ul>
      <li>Disabled: Disable IOMMU support.</li>      

      <li>Enabled: Enable IOMMU support.</li>

      <li>Auto (Default setting): Use default value for IOMMU. The default value is disable.</li>
  </ul>
 </dd> 

<dt><b>Package Power Limit Control:</b></dt> 
 <dd>
 This is a per processor Package Power Limit (PPT) value applicable for all populated processors in the system. 
 This can be set to limit the PPT to a certain value. 
 Available settings are:
  <ul>
	  <li>Auto (Default setting): Use the fused processor PPT value.</li>
	  
	  <li>Manual: Let user specifies customized processor PPT value.</li>
  </ul>
 </dd> 
 
<dt><b>Package Power Limit:</b></dt> 
 <dd>
 Set customize processor Package Power Limit (PPT) value to be used on all populated processors in the system. 
  If set to 240 = Use the 240W PPT ***PPT will be used as the ASIC power limit*** 
 </dd> 

<dt><b>APBDIS:</b></dt> 
 <dd>
  APBDis is an IO Boost disable on uncore.
  For any system user that needs to block these uncore optimizations that are impacting base core clock speed, we are exposing a method to disable this behavior called APBDis. 
  This locks the fabric clock to the non-boosted speeds.
  Available settings are:
  <ul>
      <li>0: Disable APBDIS, locks the fabric clock to the non-boosted speeds.</li>      

      <li>1: Enable APBDIS, unlocks the fabric clock to the boosted speeds.</li>

      <li>Auto (Default setting): Use default value for APBDIS. The default value is 0.</li>
  </ul>
 </dd> 

<dt><b>NUMA Nodes Per Socket:</b></dt> 
 <dd>
  Specifies the number of desired NUMA nodes per socket. 
  This option allows the user to divide the memory that each socket has into a certain number of NUMA memory nodes for optimal memory bandwidth. 
  Available settings are:
  <ul>
      <li>NPS0: It will attempt to interleave the two sockets together.</li>      

      <li>NPS1: Each processor socket will have one NUMA memory node.</li>
	  
	  <li>NPS2: Each processor socket will have two NUMA memory nodes.</li>
	  
      <li>NPS4: Each processor socket will have four NUMA memory nodes.</li>

      <li>Auto (Default setting): Use default value for NUMA nodes per socket. The default value is NPS1.</li>
  </ul>
 </dd> 

<dt><b>SMT Control:</b></dt> 
 <dd>
  This controls enable or disable the logical processor cores on the processor.
  Enable SMT Control can improve overall performance for most workloads.
  For some floating point or HPC workloads may result in highr performance if disable SMT Control.   
  Available settings are:
  <ul>
      <li>Disabled: It will disable all logical cores on the processor.</li>      

      <li>Auto (Default setting): Enable all logical cores on the processor.</li>
  </ul>
 </dd> 

<dt><b>ACPI SRAT L3 cache As NUMA Domain:</b></dt> 
 <dd>
  Controls generation of distance information in the ACPI System Locality Information Table (SLIT) and NUMA 
  proximity domains in the System Resource Affinity Table (SRAT). Enabling this feature can increase performance
  for workloads that are NUMA aware and optimized. 
  Available settings are:
  <ul>
      <li>Disabled: Not seperate each CCX within the processor as a NUMA domain.</li>      
	  <li>Enabled: Each CCX within the processor will be declared as a NUMA domain.</li>
      <li>Auto (Default setting): Use default value. Which is not seperate each CCX as a NUMA domain.</li>
  </ul>
 </dd> 

<dt><b>TSME:</b></dt> 
 <dd>
  This controls enable or disable the Transparent Secure Memory Encryption.
  Enable TSME can improve security by encrypt the data in memory.
  Disable for lower memory latency.   
  Available settings are:
  <ul>
      <li>Disabled: It will disable Transparent Secure Memory Encryption function.</li>
	  <li>Enabled: It will enable Transparent Secure Memory Encryption function.</li>       
      <li>Auto (Default setting): Enable TSME.</li>
  </ul>
 </dd> 

<dt><b>SEV Control:</b></dt> 
 <dd>
  This controls enable or disable the Secure Encrypted Virtualization.
  SEV is an extension of SME that effectively enables a per-virtual machine SME. 
  In other words, SEV enables running encrypted virtual machines in which the code and data of the VM are private to the VM and may only be decrypted within the VM itself.  
  Available settings are:
  <ul>
      <li>Disabled: It will disable Secure Encrypted Virtualization function.</li>
	  <li>Enabled (Default setting): It will enable Secure Encrypted Virtualization function.</li>       
  </ul>
 </dd> 

<dt><b>Core Performance Boost:</b></dt> 
 <dd>
  Core Performance Boost (CPB) is a dynamic frequency scaling technology implemented by AMD that allows the processor to dynamically adjust and control the processor operating frequency in certain versions of its processors which allows for increased performance when needed while maintaining lower power and thermal parameters during normal operation.  
  Available settings are:
  <ul>
      <li>Disabled: It will disable Core Performance Boost function.</li>
	  <li>Auto (Default setting): It will enable Core Performance Boost function.</li>       
  </ul>
 </dd> 

<dt><b>Memory Target Speed:</b></dt> 
 <dd>
  Specifies the memory target speed on the system in MT/s.
  Available settings are:
  <ul>
      <li>DDR3600: It will set memory at 3600 MT/s.</li>
	  <li>DDR4000: It will set memory at 4000 MT/s.</li>
	  <li>DDR4400: It will set memory at 4400 MT/s.</li>
	  <li>DDR4800: It will set memory at 4800 MT/s.</li>
	  <li>DDR5200: It will set memory at 5200 MT/s.</li>
	  <li>DDR5600: It will set memory at 5600 MT/s.</li>
	  <li>DDR6000: It will set memory at 6000 MT/s.</li>
	  <li>DDR6400: It will set memory at 6400 MT/s.</li>
	  <li>Auto (Default setting): It will set memory at highest supported speed.</li>
  </ul>
 </dd> 
 
<dt><b>DRAM Scrub Time:</b></dt> 
 <dd>
  Specifies the time to perform memory scrubbing action. It consists of reading from each computer memory location, correcting bit errors (if any) with an error-correcting code (ECC), and writing the corrected data back to the same location.
  Available settings are:
  <ul>
      <li>Disabled: It will disable memory scrubbing.</li>
	  <li>1 hour: It will set memory scrubbing action to be performed every 1 hour.</li>
	  <li>4 hours: It will set memory scrubbing action to be performed every 4 hours.</li>
	  <li>6 hours: It will set memory scrubbing action to be performed every 6 hours.</li>
	  <li>8 hours: It will set memory scrubbing action to be performed every 8 hours.</li>
	  <li>12 hours: It will set memory scrubbing action to be performed every 12 hours.</li>
	  <li>24 hours (Default setting): It will set memory scrubbing action to be performed every 24 hours.</li>
	  <li>48 hours: It will set memory scrubbing action to be performed every 48 hours.</li>
  </ul>
 </dd>  
 
<dt><b>xGMI Force Link Width:</b></dt> 
 <dd>
  Force the xGMI link width at specified value.
  Available settings are:
  <ul>
      <li>x4: Forced the xGMI link width to x4.</li>
	  <li>x8: Forced the xGMI link width to x8.</li>
	  <li>x16 (Default setting): Forced the xGMI link width to x16.</li>
  </ul>
 </dd> 

<dt><b>xGMI Max Link Width:</b></dt> 
 <dd>
  Specifies the maximum xGMI link width.
  Available settings are:
  <ul>
      <li>x4: Set the maximum xGMI link width to x4.</li>
	  <li>x8: Set the maximum xGMI link width to x8.</li>
	  <li>x16 (Default setting): Set the maximum xGMI link width to x16.</li>
  </ul>
 </dd> 

<dt><b>4-link xGMI max speed:</b></dt> 
 <dd>
  Specifies the maximum 4-link xGMI link speed between 2 CPUs.
  Available settings are: 10.667Gbps, 11Gbps, 12Gbps, 13Gbps, 14Gbps, 15Gbps, 16Gbps, 17Gbps, 18Gbps, 19Gbps, 20Gbps, 21Gbps, 22Gbps and Auto (Default setting).
 </dd> 

<dt><b>BoostFmax:</b></dt> 
 <dd>
  Specifies the maximum CPU core boost frequency value in MHz.
 </dd> 

<dt><b>ACPI CST C2 Latency:</b></dt> 
 <dd>
  C2 Latency is a value that the BIOS communicates to the OS that helps it determine when it should enter lower power states. This defines C2 latency values in microseconds. Lower C2 latency values will reduce the number of C2 transitions and C2 residency. With higher values may allow higher frequency boost and reduce idle core power. Default value is "100"
 </dd> 

<dt><b>Workload Profile: (Default = "Disabled")</b></dt> 
 <dd>
  Workload Profile loads pre-configured BIOS settings for specific workload type.
  Available options are:
  <ul>
   <li><b>Disabled</b>: Do not load any pre-configured BIOS settings.</li>
   <li><b>HPC</b>: Load BIOS settings for HPC related workloads.</li>
   <li><b>I/O</b>: Load BIOS settings for I/O intensive workloads.</li>
   <li><b>Virtualization</b>: Load BIOS settings for Virtualization related workloads.</li>
   <li><b>Telco NFVI</b>: Load BIOS settings for server runs NFVI in telecommunication environment.</li>
   <li><b>Telco NFVI-FP</b>: Load BIOS settings for server runs NFVI-FP in telecommunication environment.</li>
   <li><b>Telco FlexRAN</b>: Load BIOS settings for server runs FlexRAN in telecommunication environment.</li>
  </ul>  
 </dd>

<dt><b>SMEE:</b></dt> 
 <dd>
  This controls enable or disable the Secure Memory Encryption Enable.
  Enable SMEE can improve security by encrypt the data in memory.
  Disable for lower memory latency.   
  Available settings are:
  <ul>
      <li>Disabled: It will disable Secure Memory Encryption Enable function.</li>
	  <li>Enabled: It will enable Secure Memory Encryption Enable function.</li>       
      <li>Auto (Default setting): Enable SMEE.</li>
  </ul>
 </dd> 

</dl>

]]>
</firmware>




</flagsdescription>
